Predicting Chip-Package-Board Radiation EMI-EMC Early in the Design Cycle: Can Your EM Solver Do That ?
Consider the following scenario. Switching logic for large on-chip blocks leads to power transients. These transients find their way through solder bumps or bond wires through to the package, and through solder balls into the board. These cause not only IR drop, and voltage and ground bounce, but also cause radiation and electromagnetic interference. This radiation or EMI may couple back into the system, cause undesired interference to other system, cause unacceptable loss and noise, and may also cause the system to violate EMC rules such as those set by the FCC.
Consider a slightly diffferent scenario, associated with signal waveforms rather than switching power waveforms. Consider a differentially designed channel. Unfortunately, common modes are almost always excited due to some assymetry in channels, impedance mismatches, and complexity of geometry and environment in the chip, chip-package interface, package, package-PCB interface or within the board. This so-called “differential EMI” (i.e. arising in differentially excited and designed systems) can also create undesired crosstalk and radiated fields.
The demands on an EM solver that can be used in such a scenario are extremely challenging. 3D full-wave accuracy is key, because interface and edge-effects, especially for systems with multiple or ill-defined references, are important in EMI. Quasi-static or 2.5D solvers will not cut it in this application. At the same time, this solver needs to scale to the full chip-package-board level to allow RDL and GDS layers, full-packages, and board nets to be simulated. The speed of the solver is critical: if early design is to be enabled, several design choices need to be considered on-chip, at the package, and in the PCB including routing, decap placement, logic switching and turn-off, etc. Finally, such a solver needs to interface with on-chip noise modeling tools and SPICE, such that noise models from library characterization or worst-case switching noise can be directly integrated. These are significant challenges of accuracy, compatibility, scale, and speed, where no compromises can be made by making rudimentary assumptions on 3D full-wave EM wave behavior.
What to Ask of Your Electromagnetic Field Solver for System-Level SSN-SSO
Simultaneous switching noise (SSN) – outputs (SSO) embodies in many ways the culmination of the most difficult challenges in signal integrity (SI) and power integrity (PI) modeling. Here are some reasons why this is such a challenging problem, and one where many questions need to be asked of the electromagnetic (EM) field solvers being used to address this problem.
1. Problem definition: Some excellent resources exist on the web that describe the SSN-SSO problem, such as these public documents from Cadence, Actel, and EE Times Asia / Altera. In essence, this problem is a coupled SI-PI problem that looks at effects of signal switching on power-ground noise and of the resultant noise coupling back onto signal paths.
2. Challenges of scale: SSN-SSO simulation requires complete models for on-chip parasitics, packages, and boards with all power and ground planes and signal paths!
3. Challenges of complexity: SSN-SSO simulation needs the EM solver to model intricate complexities such as split planes, fringing, radiation, interfaces between chip and package, and package and board, via-trace transitions, effects of anti-pads, voids, metal boundaries, and complex frequency-dependent material effects.
4. Challenges of dynamic range and accuracy: One of the reasons for modeling all the complexity above is the fact that SSN-SSO simulation requires a higher dynamic range than most other SI/PI/EMI simulations. The noise levels from power to signal and signal to power are very different and both are important. The impedances of power grids (ideally as small as possible) and signal lines (typically 50 Ohms) are significantly different. Reduced voltage levels, differential signaling, and high-speed signals all contribute to the requirements for high dynamic range and high accuracy.
5. What EM simulation challenges does SSN-SSO simulation imply?
Consider again some of the challenges discussed. Frequencies will often range in the multi-GHz range due to the co-existence of signal waveforms and short rise-time-based inductive noise. This disallows the use of 3D static or quasi-static solvers, as the right phase variation and multiple resonance behavior will not be captured. Time domain SSN-SSO simulation is necessitated in SPICE-like solvers. This implies that the S-parameter models generated by the 3D full-wave solvers need to be broadband, from DC to the highest multi-GHz frequency. Considering the existence of 50 Ohm signal lines and very low impedance lines in the SI-PI cosimulation, the EM solver must not compromise on accuracy so that a high dynamic range can be properly met. The 3D nature of many discontinuties and signal-power coupling, especially in low-cost cutting-edge designs implies that 2.5D solvers that are often used for PI applications, such as those based on TEM approximations, are typically not suited for the overall SSN-SSO simulation.
6. Summary: What to ask of your EM solver!
The EM solver needs to have very stringent requirements of handling chip-package-board models and interface effects, 3D geometries and 3D full-wave field effects, accuracy and high dynamic range, the appropriate speed and scalability to handle the SSN-SSO scenario, and a broadband nature to create SPICE models and S-parameter models with both DC and high-frequency multi-GHz effects. This is extremely challenging and beyond the ability of most commercial solvers, many of which are quasi-static or 2.5D in nature. On the other hand 3D solvers tend to handle much smaller scales than needed with high simulation times!
